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Wuhan Homsh Technology Co.,Ltd.
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Q32 Iris Chip FPGA Core – Cost-Effective Single-Chip Solution for Iris Recognition and Matching

Wuhan Homsh Technology Co.,Ltd.
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Q32 Iris Chip FPGA Core – Cost-Effective Single-Chip Solution for Iris Recognition and Matching

Brand Name : HOMSH

Place of Origin : China

Certification : ISO9001

MOQ : 1

Delivery Time : 5-9day

Payment Terms : T/T

Model Number : Q32

Iris Localization Search Area : 768x768 pixels

Supported Iris Radius Pixel Range : 60 ~ 160 pixels

Supported Minimum Image Resolution : 2lp/mm

Encoding Speed : 50ms per image

Matching Speed : Up to 12000 templates/s

Product Name : Iris Chip

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Product Overview

The Q32 chip takes Homsh Technology’s PhaseIrisTM 3rd-generation iris hard-core engine technology as its core, providing a cost-effective single-chip solution for iris recognition and matching applications. It serves as a high-cost-performance option in the iris recognition application industry.

Performance Features

1. Core Acceleration Technology: Adopts PhaseIris Gen3 iris hard-core acceleration technology (area optimization mode) with a streamlined matching engine (matching engine) ×3, balancing performance and cost.

2. Interface and Camera Support:

Provides GPIO/IIC interfaces.

Supports 2 parallel-port camera inputs, with a maximum support of 5 million pixels; integrates ISP, supporting functions such as automatic exposure, channel balance, and image cropping.

3. Matching and Image Output:

Supports QSPI Flash read template matching, up to 7,000 templates/s.

Supports DVP digital image output, up to 2 million pixels.

4. USB Interface Matching: When an external USB2.0 interface is connected, it supports real-time transmission template matching, up to 12,000 templates/s.

Application Fields

● Smart Terminal Security: Suitable for devices such as smart door locks, safes, and private storage cabinets to realize iris recognition-based identity verification and secure access.

● Lightweight Information Systems: Can be used in scenarios such as information login terminals to provide iris-level security for personal private data access.

Why Choose Q32?

1. Outstanding Cost-Effectiveness: Based on PhaseIris Gen3 hard-core technology (area optimization mode) and a streamlined matching engine, it achieves a balance between performance and cost, serving as a high-cost-performance solution in the industry.

2. Dual-Camera and Diverse Output: Supports 2 parallel-port camera inputs and DVP digital image output, adapting to more complex image acquisition and output scenarios.

3. Multi-Scenario Matching Capability: With QSPI Flash matching (up to 7,000 templates/s) and USB2.0 real-time matching (up to 12,000 templates/s), it meets the needs of both offline and online iris recognition scenarios.

4. High Security and Precision: FAR < , FRR < , and full-process iris algorithms (localization, liveness detection, matching, etc.) ensure the security and accuracy of identity verification.

As a professional enterprise in the biometric sector, Wuhan Homsh Technology drives secure authentication through technological innovation. Leveraging proprietary core algorithms, end-to-end technical capabilities, and high-precision hardware expertise, we provide professional support for our full range of biometric products, including iris recognition and vein recognition.

We cater to the needs of global industries like finance and security, offering technical consultation, custom development, and round-the-clock after-sales support. We look forward to partnering with global counterparts to build a secure authentication ecosystem via biometric technology and empower industrial digital upgrading.

Technical Parameters:

Parameter and Feature Value or Support
Chip Model Q32
False Acceptance Rate (FAR) < 10-7
False Rejection Rate (FRR) < 10-3
Iris Localization Search Area 768x768 pixels
Supported Iris Radius Pixel Range 60 ~ 160 pixels
Supported Minimum Image Resolution 2lp/mm
Encoding Speed 50ms per image
Matching Speed Up to 12000 templates/s
Matching Engine Supports Axi4-stream bus interface, 4-bit data width, non-pipelined structure
Algorithm Parameter Register Set Real-time configuration, supports Axi4-lite/apb bus interface
Encoding Engine Image cache supports external shared memory, encoding engine RAM interface width configurable as 32/16/8-bit, interface mode: master
Iris Localization
Liveness Detection
Iris Clarity Assessment
Iris Segmentation
2D Image Transformation
Feature Extraction
Iris Matching
Q32 Iris Chip FPGA Core – Cost-Effective Single-Chip Solution for Iris Recognition and Matching



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Q32 Iris Chip FPGA Core – Cost-Effective Single-Chip Solution for Iris Recognition and Matching Images

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